1. Technical Field of the Invention
The present invention relates to integrated circuits and more particularly to semiconductor devices comprising at least one transistor, preferably an MOS transistor, of improved electrical performance.
2. Description of Related Art
Conventionally, MOS transistors are formed in an active zone of a semiconductor substrate isolated from the rest of the substrate by an isolation region, for example a region of the STI (Shallow Trench Isolation) type, by the formation of source and drain regions, which define a channel between them, and of a gate region that extends above this channel.
MOS transistors are generally covered with an etch stop layer, for example an edge-free nitride layer that may be formed following a PECVD (Plasma Enhanced Chemical Vapor Deposition) operation. This etch stop layer is then covered with a dielectric layer in which contact holes are etched so as to electrically connect the source, drain and gate regions of the transistor.
The etch stop layer may therefore represent a detection point during the operation of etching the contact holes in the dielectric layer. More particularly, detection of this layer allows the etching of the contact holes to be continued in order to reach the silicon zones of the transistor, for example for a predetermined time.
The residual stress of the etch stop layer allows the electrical performance of a transistor, in particular the current that flows between the drain and the source in the “on” state, to be modified. This current may be increased or decreased according to the mechanical stress level applied to the transistor. This is because the stop layer makes it possible to induce a local curvature in the substrate of the semiconductor device, which generates a mechanical stress in the channel. Such a stress acts on the mobility of the carriers and consequently on the electrical performance of the transistor.
In particular, it is found that an etch stop layer inducing compression improves the operation of a pMOS-type transistor but at the same time degrades the operation of an nMOS-type transistor. Conversely, an etch stop layer that induces tension improves the operation of an nMOS-type transistor, but degrades the operation of a pMOS-type transistor. Thus, any improvement made to one type of transistor is made to the detriment of the other type of transistor.
To improve the electrical performance of nMOS and pMOS transistors at the same time, a process has already been proposed in document IBM IEDM 2004 which consists in producing a semiconductor device based on MOS transistors, in which a first etch stop layer in tension covers at least one nMOS transistor and a second etch stop layer in compression covers at least one pMOS transistor.
Such a process consists in depositing a first etch stop layer in tension over all of the transistors of the device and then in carrying out photolithography and etching steps so as to remove the parts of the stop layer that cover the pMOS transistors. This process then involves the deposition of a second etch stop layer in compression over all of the transistors and photolithography and etching steps being carried out on the parts of the stop layer covering the nMOS transistors.
This process thus has the drawback of involving etching steps that are difficult to implement and may damage the transistors of the device.
FR 2 846 789 discloses a semiconductor device based on MOS transistors, in which the etch stop layer includes a first layer of material having a first residual stress level covering some of the transistors of the device, for example a pMOS transistor, and a second layer of material that has a second residual stress level covering all of the transistors of the device, namely both pMOS transistors and nMOS transistors.
In this particular structure, the first layer and the second layer of the material of the etch stop layer are chosen so as to have residual stress levels that are of opposite sign so as to obtain simultaneous improvement in the electrical performance on both types of transistor.
Thus, in this structure, a pMOS transistor may be covered both with a first layer of material in compression and with a second layer of material in tension, the superposition of these two layers inducing compression in the channel of this transistor, improving the mobility of the carriers, whereas only the second layer of material inducing tension covers the nMOS transistor.
However, this process has inter alia the drawback of involving a photolithography step followed by at least one etching step which are difficult to implement.
In particular, this process involves a step of etching the first layer of material deposited, for example, on an nMOS transistor, which is difficult to implement as this step may damage the transistor.
Furthermore, the thickness of the layers is not uniform above the various types of transistor, which may result in difficulties in etching the contact holes in order for the silicon zones of the transistor to be electrically connected.
In view of the foregoing, the object of the invention is in particular to produce a semiconductor device comprising at least one MOS transistor, in which it is possible for the residual stress level of an etch stop layer to be adapted in a discriminating manner according to the nature of the transistors that it covers, while minimizing the number of photolithography and etching steps.